A module port name can supersede a named intermediate signal in generated outputs

[mkorbel1]

Describe the bug

If a signal is given an explicit name and used to connect two ports of other modules with non-unpreferred port names, then the name of the signal in generated SystemVerilog may be one of the port names instead of the given name. For users who care a lot about the readability and details of generated output, this can be confusing and undesirable.

To Reproduce

Create two modules and connect an input from one to an output of another with a named signal, then generate verilog and inspect the signal name.

Expected behavior

The connecting signal in the top module will be the explicitly given name.

Actual behavior

One of the module port names will be used for the intermediate signal.