[SYCL][HIP] Implement PI_DEVICE_INFO_ATOMIC_64 for HIP

[pgorlani]

This patch implements aspect::atomic64 by querying the information related to the 64-bit integer atomic operations. At the moment, the floating-point atomics are not supported at all (single and double precision) for AMD devices. The SYCL_USE_NATIVE_FP_ATOMICS is not set for AMD, and the atomc_ref class handles the lack of double and single precision atomic operations.

We may want to revisit this implementation when the floating-point atomics will be supported by AMD too.

However, I think this is not necessary for three reasons:

1. the atomic64 aspect "Indicates that kernels submitted to the device may perform 64-bit atomic operations." It expresses a possibility, not specifying any kind of operations or data types.
2. the SYCL specifications for atomic_ref say "For floating-point types, the member functions of the atomic_ref class may be emulated, and may use a different floating-point environment to ..." implying that the floating-point operations in atomic_ref do not need to be supported natively by the hardware.
3. both L0 and OpenCL backends check only for 64-bit integer atomics.

This solves https://github.com/intel/llvm/issues/5570, https://github.com/intel/llvm/issues/6054, and allows to re-enable tests in https://github.com/intel/llvm-test-suite/pull/861.

[sergey-semenov]

@pgorlani The changes looks good, but there are now unexpected passes in testing. Is there an llvm-test-suite PR for enabling those two tests?

[pgorlani]

Hi @sergey-semenov, here is https://github.com/intel/llvm-test-suite/pull/1094.

[sergey-semenov]

/verify with https://github.com/intel/llvm-test-suite/pull/1094

[pgorlani]

Hi @sergey-semenov, is it possible to merge this PR?

Thanks!