[SYCL][Doc] Add SYCL_INTEL_FPGA_data_flow_pipes_properties extension

[pcolberg]

See also https://github.com/intel/llvm/pull/5838

Cc: @mkinsner @GarveyJoe @aditikum @rho180 @zibaiwan

[bader]

Interesting! A minor remark: do not use uppercase like AXI and AVALONin the API but just the lowercase. Otherwise, what to do if the programmer writes:

// Use the AXI protocol in the following interface
#define AXI 1

and then the havoc happens. And we all know how FPGA programmers love low-level C and preprocessor. ;-)

FYI, there is a pull request suggesting a new guideline for naming various things - https://github.com/intel/llvm/pull/5843. Feel free to contribute your thoughts there.