Sean Cross

Same configuration as last time. It's using `linuxFull()` as the CSR config.

https://github.com/xobs/VexRiscv-verilog/blob/master/src/main/scala/vexriscv/GenHaD.scala

gdb will read the `$pc` in order to know where it is. That way it can do things like trace the interrupt handler when an interrupt occurs. With Vex, it...

Sorry for the noise -- the other issue was completely unrelated and appears to be a bug in Linux where it assumes memory is cleared before it clears the BSS....

Testing by having blockram at address 0x10000000, and loading the following binary. Commands reproduced here so I can remember them in the future - wfitest.S: ```asm .global _start _start: csrw...

> > > @xobs I'm guessing the clear should be sent upstream to the RISC-V Linux? I'm not sure how you'd do that. They make an assumption that the memory...

Self-refilled should be fine, whichever has the lower gate count is preferable.

I know this isn't the right place to hold a discussion about it, but we use the DebugPlugin by placing it on the general [wishbone] memory bus and tunneling it...

Note that it also fails on Darwin, linux-mips, and linux-mips64: https://travis-ci.org/xobs/wishbone-utils/builds/578424583

After seeing your announcement, I've started looking into this. So far I have it listing windows, and I've started working on the capture steps. Current issues are: 1. Convert is...