riscv-config
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riscv-software-src
RISC-V Configuration Validator
I would like to add V support to riscv-config, this is the first PR.
This issue is a parallel issue to: https://github.com/riscv/sail-riscv/issues/192 Following is the text of that issue: Reference: Priv Spec., Table 3.7 "Synchronous exception priority in decreasing priority order." The priority of...
isa_yaml with RV64IMAFDCSU gives isa_checked.yaml with the following registers as accessible. - VSSTATUS - VSIE - VSIP - VSSCRATCH - VSEPC - VSTVAL - VSCAUSE - VSTVEC - VSATP It...
Validated string should be presented as a suggestion along with an error message. https://github.com/riscv-software-src/riscof/issues/67#issuecomment-1277393681 rv32imcfzk_xfoo -> RV32IMCF_Zicsr_Zk RV32I_M_F_Zicsr -> RV32IMFZicsr RV32I2p0M2F_Zicsr -> RV32IMFZicsr Invalid ISA strings (i.e. wrong order) may...
https://github.com/riscv-software-src/riscv-config/blob/d9189066ae0dca46ad2d768c9d47ff3486833759/riscv_config/isa_validator.py#L93 Similar to #108
https://github.com/riscv-software-src/riscv-config/blob/3f3a3b8a9c8fc88294ac5b4ac5c1ae9c92fa1305/riscv_config/isa_validator.py#L100
The spec mentions the following constraint on the misa extensions: ``` Writing misa may increase IALIGN, e.g., by disabling the “C” extension. If an instruction that would write misa increases...
According to the Spec mtval is a WARL field. However, a platform has a luxury to completely specify which exceptions must set mtval informatively and which may unconditionally set it...
The "nmi" field should be optional, but is required, as can be seen in `schema_platform.yaml`. Original issue: riscv-non-isa/riscv-arch-test#279
