riscv-dbg
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pulp-platform
RISC-V Debug Support for our PULP RISC-V Cores
Provides a more robust alternative to `read_dmi()`, which does not rely on a fixed delay, but rather calls `read_dmi()` until the read is successful and automatically adjusts the delay with...
During bring-up of riscv-dbg on my Verilator testbench I found that TRST was asserted after running the dm_debug.cfg openocd script. A bit of investigation showed that TRST got asserted by...
Hi, I just downloaded this repo it looks interesting thanks for creating it! However I have a problem when trying to run it: > cd riscv-dbg/tb > make veri-run >...
Converted the Travis CI workflow to GitHub Actions. Although there seem to be some issues while building verilator. ``` In file included from ../V3ParseLex.cpp:36:0: V3Lexer_pregen.yy.cpp:369:10: fatal error: FlexLexer.h: No such...
As reported in #80, there is an endless simulation loop in ./src/dm_mem.sv. In the existing code: - always_comb "p_hart_ctrl_queue" has a dependency on "halted_aligned" and produces "go", "resume", and "cmdbusy_o"...
A timeout waiting for an SBA access to complete can be signaled with `SBCS[SBERROR] == 1`, according to the RISCV debug spec. The timeout value can be set either as...
Alternative fix for the '32-bit slave access to Abstract Data' issue reported in https://github.com/pulp-platform/riscv-dbg/pull/27 more inline with the writing style recommended by @bluewww Signed-off-by: Arjan Bink
can someone explain does 'cause' field in the dcsr register should be set to 0 if it is returing to machine mode from normal mode
There is currently a new version (not yet ratified) of the debug spec: Version 1.0.0-STABLE b992bc5275a398023250bf974a842e1c60ea3716 This contains updates specific to both core implementation and to the debug module.
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RISC-V Debug Support for our PULP RISC-V Cores