cv32e40p

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This PR resolves SV compile errors and warnings flagged by dsim:

• bhv/cv32e40p_rvfi.sv: nonblocking assignments to automatic variables are not allowed (object variables are automatic by default). Dsim won't compile this but I expect VCS does.
• bhv/cv32e40p_tb_wrapper.sv: dsim warns about several width mismatches. I did not resolve this, but they are flagged with FIXMEs.

Hi @MikeOpenHWGroup - you should download Verible, checkout the version mentioned in the README and run verible (the script is in the util folder)

Done. Verible wanted to make a lot of changes to both bhv and rtl files. I only pushed in the verible-ized versions of the files modified in this pull-request, namely bhv/cv32e40p_rvfi.sv and bhv/cv32e40p_tb_wrapper.sv.

Done. Verible wanted to make a lot of changes to both bhv and rtl files. I only pushed in the verible-ized versions of the files modified in this pull-request, namely bhv/cv32e40p_rvfi.sv and bhv/cv32e40p_tb_wrapper.sv.

probably you.are not using the right version, indeed the CI still fails. if you want we can set a meeting and fix it

Ha! I resubmitted using verible-verilog-format version v0.0-1149-g7eae750 and it seems to work.