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linuxboot
T430s support
The config and binary files for the T430s maximized.
Tested it and anything works well.
It only assumes that the installed SOIC-8 chip is a MX25L12835F/MX25L12845E/MX25L12865E. That's because flashrom detects two chips and won't read or write. So the chip needs to be specified in the option.
~Do you wish a remark about this in the tutorial in the Heads wiki?~
closes #723 closes #1017
@Siproqu
user@heads-tests:~/heads$ git diff
diff --git a/config/coreboot-t430s-maximized.config b/config/coreboot-t430s-maximized.config
index 185dc9d..c5b3b7e 100644
--- a/config/coreboot-t430s-maximized.config
+++ b/config/coreboot-t430s-maximized.config
@@ -4,9 +4,9 @@ CONFIG_STATIC_OPTION_TABLE=y
CONFIG_VENDOR_LENOVO=y
CONFIG_NO_POST=y
CONFIG_CBFS_SIZE=0xB80000
-CONFIG_IFD_BIN_PATH="../../blobs/t430s/ifd.bin"
-CONFIG_ME_BIN_PATH="../../blobs/t430s/me.bin"
-CONFIG_GBE_BIN_PATH="../../blobs/t430s/gbe.bin"
+CONFIG_IFD_BIN_PATH="../../blobs/xx30/ifd.bin"
+CONFIG_ME_BIN_PATH="../../blobs/xx30/me.bin"
+CONFIG_GBE_BIN_PATH="../../blobs/xx30/gbe.bin"
CONFIG_HAVE_IFD_BIN=y
CONFIG_BOARD_LENOVO_T430S=y
CONFIG_LINUX_COMMAND_LINE="intel_iommu=igfx_off quiet"
Not sure why the extraction script and cleaner scripts were duplicated under another blobs directory. Was there anything wrong with xx30 script for t430s?
Changing the above, and calling the proper blobs directory script under xx30 should work. Then the above changes will point to those blobs, not requiring them to be hosted under github (me, gbe being the blobs, where ifd can be hosted without legal problems). Otherwise people are getting really confused about the multiplication of blobs and what to do with them, for example.
Doing so, t430s builds:
2021-08-24 14:33:36-04:00 MAKE coreboot
2021-08-24 14:34:45-04:00 DONE coreboot
# Use coreboot.rom, because custom output files might not be processed by cbfstool
"/home/user/heads/build/coreboot-4.13/t430s-maximized/cbfstool" "/home/user/heads/build/coreboot-4.13/t430s-maximized/coreboot.rom" print
FMAP REGION: COREBOOT
Name Offset Type Size Comp
cbfs master header 0x0 cbfs header 32 none
fallback/romstage 0x80 stage 86796 none
cpu_microcode_blob.bin 0x15400 microcode 26624 none
fallback/ramstage 0x1bc80 stage 119643 none
config 0x39040 raw 819 none
revision 0x393c0 raw 697 none
fallback/dsdt.aml 0x396c0 raw 14615 none
cmos.default 0x3d040 cmos_default 256 none
vbt.bin 0x3d180 raw 1409 LZMA (4459 decompressed)
cmos_layout.bin 0x3d740 cmos_layout 1932 none
fallback/postcar 0x3df40 stage 27288 none
fallback/payload 0x44a40 simple elf 7287751 none
(empty) 0x737e40 null 4357976 none
bootblock 0xb5fdc0 bootblock 65536 none
2021-08-24 14:34:45-04:00 INSTALL build/coreboot-4.13/t430s-maximized/coreboot.rom => build/t430s-maximized/heads-t430s-maximized-v0.2.0-1051-g0e962d6-dirty.rom
bda6dac7313bf9dfbe290eb0a0877580795d3b60900e3de6891e8214a9371326 build/t430s-maximized/heads-t430s-maximized-v0.2.0-1051-g0e962d6-dirty.rom
4b3be2b552ab6b60df7291bfbd819d9b92f88641662472e0ebd8ca7fc27a4c63 /home/user/heads/build/gawk-4.2.1/gawk
Can you test outcome and modify this PR accordingly?
On another note, I am not sure why specifying the chip is necessary. Have you tried not specifying anything? Internal flashing should work with newer version of flashrom. This is not the case? What is the output on screen when not specifying -c and internally flashing?
Thanks!
Not sure why the extraction script and cleaner scripts were duplicated under another blobs directory. Was there anything wrong with xx30 script for t430s?
Thanks for the hint. Will remove them.
I am not sure why specifying the chip is necessary. Have you tried not specifying anything?
Yes. Unfortunately flashrom detects two chips and won't proceed reading/writing if non of them is specified. It requested the -c option to be set.
Changing the above, and calling the proper blobs directory script under xx30 should work. Then the above changes will point to those blobs, not requiring them to be hosted under github (me, gbe being the blobs, where ifd can be hosted without legal problems). Otherwise people are getting really confused about the multiplication of blobs and what to do with them, for example.
The ifd.bin and gbe.bin differed significantly to the ones of the xx30.
As of the T430s spec the Ethernet NIC is, just as the xx30 series, an 82579LM. But diffs of both blobs have a lot of different bytes set (see below). The T430s has even some padding bytes set where the xx30 does not.
The diff of the xx30/ifd.bin and the t430s/ifd.bin reveals some differences as well. ~5bits are set differently and the EC firmware version string is different (xx30: G1RM42WW.8.0.12.1498.12M B.SIGNED vs. T430s: G1RN14WW.8.1.30.1350.16M B.SIGNED)
Because all of this I hesitated to flash Heads with the xx30 blobs. Since the T430s is the machine I'm working on and flashing it externally does not work at the moment, bricking it is not really an option.
Diff of xx30 gbe and T430s gbe
diff --git a/xx30-gbe-out b/t430s-gbe-out
index b514ad4..39242c1 100644
--- a/xx30-gbe-out
+++ b/t430s-gbe-out
@@ -9,9 +9,9 @@
"reserved_x03" = 0x800,
"reserved_x04" = 0xffff,
"imageversioninfo_x05" = 0xd3,
- "reserved_x06" = 0xffff,
- "reserved_x07" = 0xffff,
- "pba_low_x08" = 0xffff,
+ "reserved_x06" = 0x149,
+ "reserved_x07" = 0x8000,
+ "pba_low_x08" = 0x1000,
"pba_high_x09" = 0xffff,
"pci_loaddeviceid_0" = 0x1,
"pci_loadsubsystemid_1" = 0x1,
@@ -20,8 +20,8 @@
"pci_pmenable_6" = 0x1,
"pci_auxpwr_7" = 0x1,
"pci_reserved_8" = 0x10,
- "subsystemid_x0B" = 0x0,
- "subsystemvendorid_x0C" = 0x8086,
+ "subsystemid_x0B" = 0x21f3,
+ "subsystemvendorid_x0C" = 0x17aa,
"deviceid_x0D" = 0x1502,
"reserved_x0E" = 0x0,
"reserved_x0F" = 0x0,
@@ -37,11 +37,11 @@
"sicw_forcespeed_4" = 0x0,
"sicw_reserved_5" = 0x0,
"sicw_phydeviceype_6" = 0x0,
- "sicw_reserved_8" = 0x1,
+ "sicw_reserved_8" = 0x0,
"sicw_phy_enpwrdown_9" = 0x0,
- "sicw_reserved_10" = 0x1,
- "sicw_macsecdisable_13" = 0x1,
- "sicw_sign_14" = 0x2,
+ "sicw_reserved_10" = 0x0,
+ "sicw_macsecdisable_13" = 0x0,
+ "sicw_sign_14" = 0x0,
"ecw1_extcfgptr_0" = 0x28,
"ecw1_oemload_12" = 0x1,
"ecw1_phyload_13" = 0x1,
@@ -94,28 +94,28 @@
"reserved_x26_12" = 0x0,
"reserved_x26_14" = 0x1,
"reserved_x26_15" = 0x0,
- "reserved_x27" = 0x80,
+ "reserved_x27" = 0x886,
"offset_x28" = 0x0,
"offset_x29" = 0x0,
- "offset_x2A" = 0x0,
+ "offset_x2A" = 0x7,
"offset_x2B" = 0x0,
"offset_x2C" = 0x0,
"offset_x2D" = 0x0,
"offset_x2E" = 0x0,
- "offset_x2F" = 0x0,
+ "offset_x2F" = 0xffff,
"pxe30_protocolsel_0" = 0x0,
"pxe30_reserved_2" = 0x0,
- "pxe30_defbootsel_3" = 0x3,
+ "pxe30_defbootsel_3" = 0x0,
"pxe30_reserved_5" = 0x0,
- "pxe30_prompttime_6" = 0x3,
- "pxe30_dispsetup_8" = 0x0,
+ "pxe30_prompttime_6" = 0x0,
+ "pxe30_dispsetup_8" = 0x1,
"pxe30_reserved_9" = 0x0,
"pxe30_forcespeed_10" = 0x0,
"pxe30_forcefullduplex_12" = 0x0,
"pxe30_reserved_13" = 0x0,
"pxe30_reserved_14" = 0x0,
- "pxe31_disablemenu_0" = 0x1,
- "pxe31_disabletitle_1" = 0x1,
+ "pxe31_disablemenu_0" = 0x0,
+ "pxe31_disabletitle_1" = 0x0,
"pxe31_disableprotsel_2" = 0x0,
"pxe31_disbootorder_3" = 0x0,
"pxe31_dislegacywak_4" = 0x0,
@@ -124,9 +124,9 @@
"pxe31_ibootagentmode_8" = 0x0,
"pxe31_contretrydis_11" = 0x0,
"pxe31_reserved_12" = 0x0,
- "pxe31_signature_14" = 0x2,
- "pxe32_buildnum_0" = 0x28,
- "pxe32_minorversion_8" = 0x2,
+ "pxe31_signature_14" = 0x1,
+ "pxe32_buildnum_0" = 0x51,
+ "pxe32_minorversion_8" = 0x3,
"pxe32_majorversion_12" = 0x1,
"pxe33_basecodepresent_0" = 0x1,
"pxe33_undipresent_1" = 0x1,
@@ -134,7 +134,7 @@
"pxe33_efiundipresent_3" = 0x0,
"pxe33_iscsi_4" = 0x0,
"pxe33_reserved_5" = 0x0,
- "pxe33_signature_14" = 0x2,
+ "pxe33_signature_14" = 0x1,
"pxe_padding0" = 0xffff,
"pxe_padding1" = 0xffff,
"pxe_padding2" = 0xffff,
@@ -144,9 +144,9 @@
"pxe_padding6" = 0xffff,
"pxe_padding7" = 0xffff,
"pxe_padding8" = 0xffff,
- "pxe_padding9" = 0xffff,
+ "pxe_padding9" = 0x100,
"pxe_paddinga" = 0xffff,
- "checksum_gbe" = 0x8400,
+ "checksum_gbe" = 0x926e,
"g3_s5_phy_conf0" = 0x0,
"g3_s5_phy_conf1" = 0x0,
"g3_s5_phy_conf2" = 0x0,
@@ -179,78 +179,78 @@
"padding7" = 0xff,
"padding8" = 0xff,
"padding9" = 0xff,
- "paddinga" = 0xff,
- "paddingb" = 0xff,
- "paddingc" = 0xff,
- "paddingd" = 0xff,
- "paddinge" = 0xff,
- "paddingf" = 0xff,
- "padding10" = 0xff,
- "padding11" = 0xff,
- "padding12" = 0xff,
- "padding13" = 0xff,
- "padding14" = 0xff,
- "padding15" = 0xff,
- "padding16" = 0xff,
- "padding17" = 0xff,
- "padding18" = 0xff,
- "padding19" = 0xff,
- "padding1a" = 0xff,
- "padding1b" = 0xff,
- "padding1c" = 0xff,
- "padding1d" = 0xff,
- "padding1e" = 0xff,
- "padding1f" = 0xff,
- "padding20" = 0xff,
- "padding21" = 0xff,
- "padding22" = 0xff,
- "padding23" = 0xff,
- "padding24" = 0xff,
- "padding25" = 0xff,
- "padding26" = 0xff,
- "padding27" = 0xff,
- "padding28" = 0xff,
- "padding29" = 0xff,
- "padding2a" = 0xff,
- "padding2b" = 0xff,
- "padding2c" = 0xff,
- "padding2d" = 0xff,
- "padding2e" = 0xff,
- "padding2f" = 0xff,
- "padding30" = 0xff,
- "padding31" = 0xff,
- "padding32" = 0xff,
- "padding33" = 0xff,
- "padding34" = 0xff,
- "padding35" = 0xff,
- "padding36" = 0xff,
- "padding37" = 0xff,
- "padding38" = 0xff,
- "padding39" = 0xff,
- "padding3a" = 0xff,
- "padding3b" = 0xff,
- "padding3c" = 0xff,
- "padding3d" = 0xff,
- "padding3e" = 0xff,
- "padding3f" = 0xff,
- "padding40" = 0xff,
- "padding41" = 0xff,
- "padding42" = 0xff,
- "padding43" = 0xff,
- "padding44" = 0xff,
- "padding45" = 0xff,
- "padding46" = 0xff,
- "padding47" = 0xff,
- "padding48" = 0xff,
- "padding49" = 0xff,
- "padding4a" = 0xff,
- "padding4b" = 0xff,
- "padding4c" = 0xff,
- "padding4d" = 0xff,
- "padding4e" = 0xff,
- "padding4f" = 0xff,
- "padding50" = 0xff,
- "padding51" = 0xff,
+ "paddinga" = 0x2,
+ "paddingb" = 0x34,
+ "paddingc" = 0x30,
+ "paddingd" = 0x0,
+ "paddinge" = 0x14,
+ "paddingf" = 0x2,
+ "padding10" = 0x31,
+ "padding11" = 0x0,
+ "padding12" = 0x36,
+ "padding13" = 0x38,
+ "padding14" = 0x30,
+ "padding15" = 0x0,
+ "padding16" = 0x12,
+ "padding17" = 0x0,
+ "padding18" = 0x31,
+ "padding19" = 0x0,
+ "padding1a" = 0x37,
+ "padding1b" = 0x38,
+ "padding1c" = 0x30,
+ "padding1d" = 0x0,
+ "padding1e" = 0x17,
+ "padding1f" = 0x0,
+ "padding20" = 0x31,
+ "padding21" = 0x0,
+ "padding22" = 0x38,
+ "padding23" = 0x38,
+ "padding24" = 0x30,
+ "padding25" = 0x0,
+ "padding26" = 0x1d,
+ "padding27" = 0x0,
+ "padding28" = 0x31,
+ "padding29" = 0x0,
+ "padding2a" = 0x1a,
+ "padding2b" = 0x84,
+ "padding2c" = 0x32,
+ "padding2d" = 0x0,
+ "padding2e" = 0x4c,
+ "padding2f" = 0x52,
+ "padding30" = 0x3a,
+ "padding31" = 0x0,
+ "padding32" = 0x0,
+ "padding33" = 0x0,
+ "padding34" = 0x32,
+ "padding35" = 0x0,
+ "padding36" = 0x40,
+ "padding37" = 0x60,
+ "padding38" = 0x1f,
+ "padding39" = 0x0,
+ "padding3a" = 0x4,
+ "padding3b" = 0xd1,
+ "padding3c" = 0x11,
+ "padding3d" = 0x0,
+ "padding3e" = 0x80,
+ "padding3f" = 0x60,
+ "padding40" = 0x1f,
+ "padding41" = 0x0,
+ "padding42" = 0x0,
+ "padding43" = 0xcc,
+ "padding44" = 0x10,
+ "padding45" = 0x0,
+ "padding46" = 0x80,
+ "padding47" = 0x8,
+ "padding48" = 0x15,
+ "padding49" = 0x0,
+ "padding4a" = 0xd5,
+ "padding4b" = 0x35,
+ "padding4c" = 0x13,
+ "padding4d" = 0x0,
+ "padding4e" = 0x0,
+ "padding4f" = 0x0,
+ "padding50" = 0x1f,
+ "padding51" = 0x0,
"padding52" = 0xff,
"padding53" = 0xff,
"padding54" = 0xff,
@@ -531,906 +531,906 @@
"padding167" = 0xff,
[a lot more padding with some bytes set.]
Tested it and anything works well.
Sorry for not being precise here.
What was tested:
- Reset of the TPM
- TOTP generation
- signing of /boot
- adding a gpg key to the firmware + flashing it.
Not tested:
- HOTP
- Storing disk encryption key in TPM.
Bugs:
Also notable is that the laptop screen does not gets initialized properly when it boots while connected to a docking station with a monitor. The screen of the laptop has the wrong resolution and weird colors. The docking station screen shows everything fine. It is not really game breaking, because one can simply disconnect the laptop from the docking station while booting.
@Siproqu Would you be willing to rebase on master and bump coreboot to 4.18 as per #1234 ?