CSI2Rx

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Hi! Sorry, making this a 'new issue' hoping you get a notification of it: this Verilog code package has issues with place and routing on the icebreaker board (ICE40UP5k) through...

ouch3994

ice40?

6

David is ice40 permanently stalled? I do appreciate you are heavily committed on other open source initiatives!! have potential interest and/or project, any chance of a headsup? thanks again

peepo

Hello I have two questions. 1. D-PHY spec operates in two modes, HS and low power which use different IO standards such as differential and single ended. How can we...

luxapana

IO standard interface problem

1

I have adopt about different IO standard. MIPI CSI 2 has 200mv swing voltage at HS mode**(SLVS200)** but, is it possible to capture these low voltage differential signal with FPGA?...

Takayama-Lissajous