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Litex appears to consider iospace to be 0x80000000 and above when configuring a vexriscv cpu.

Unfortunately this is only true sometimes:

https://github.com/litex-hub/pythondata-cpu-vexriscv/blob/master/pythondata_cpu_vexriscv/verilog/src/main/scala/vexriscv/GenCoreDefault.scala#L161

        if (linux) new MmuPlugin(
          ioRange = (x => x(31 downto 28) === 0xB || x(31 downto 28) === 0xE || x(31 downto 28) === 0xF)
        ) else if (argConfig.pmpRegions > 0) new PmpPlugin(
          regions = argConfig.pmpRegions, granularity = argConfig.pmpGranularity, ioRange = _.msb
        ) else new StaticMemoryTranslatorPlugin(
          ioRange      = _.msb
        ),

For the "linux" configuration, io space is the 256MB windows at 0xB0000000, 0xE0000000, and 0xF0000000.

The liteeth peripheral ends up (by default) with its SRAM packet buffers at 0x80000000 and you end up needing to use the vexriscv dcache invalidate instruction (0x500F) to avoid reading stale packet data.

If you manually configure that region at 0xE0000000, for example (via mem_map), this problem goes away (the ethernet tx/rx buffers are no longer cached).

Ahhh that's probably some legacy from old times.

I would say we can change this into the following without issues (vexriscv_smp ref): https://github.com/SpinalHDL/VexRiscv/blob/1c3b9e93a2167bdc1c5c9fa44841d13d7611db19/src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexCluster.scala#L152

swetland do you wanna give a try / pr ? Else i can do it ^^