Support for CS active high

CS lines can now be active high. Ideas taken from https://github.com/eblot/pyftdi/pull/86/files

Main difference is that we can individually select which CS lines that shall be active high. This is done using a bitfield.

I have a proprietary device with active high CS line, and you PR gave me great service.

Thank you very much for your job. It would be nice to see this feature merged.

Glad to hear that someone found it useful.

I am in the same situation, I also need this for a proprietary design. I would also like to see it merged into the main project.

Will do but I think a couple of changes are required. I lack time at the moment :-(

No worries. And thanks for the time you have put into the project.

I agree that an iterable is better, good idea. Not sure what you mean by cross-checking, do you mean check that we are not using non-CS-configured pins? This is done already.

I looked at writing a small unit test, but it looked like the existing ones were designed to run against a particular hardware configuration (expects to find chips at different CS locations). Maybe I misunderstood? I wasn't sure how to proceed. I will take another look.

I pushed the fixes I made a few days ago. I am not familiar with the work flow on github, and I think it is not exactly intuitive... Am I expected to do something else?

I also just 'resolved' the comments you made, which seemed the right thing to do. Please bear with me, I am a noob. :)