python-fpga-interchange

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When VPR is loading the testarch it generates the following warnings:

# Loading Architecture Description
Use FPGA Interchange device
Warning 1: Model 'DFFS' input port 'C' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 2: Model 'DFFS' input port 'S' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 3: Model 'DFFS' input port 'D' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 4: Model 'DFFS' output port 'Q' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 5: Model 'DFFR' input port 'C' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 6: Model 'DFFR' input port 'R' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 7: Model 'DFFR' input port 'D' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 8: Model 'DFFR' output port 'Q' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 9: Model 'IB' input port 'P' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 10: Model 'IB' output port 'I' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 11: Model 'OB' input port 'O' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 12: Model 'OB' output port 'P' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
# Loading Architecture Description took 0.02 seconds (max_rss 17.4 MiB, delta_rss +2.9 MiB)

But when looking at the script that generates the testarch the timing data should be available, https://github.com/chipsalliance/python-fpga-interchange/blob/master/fpga_interchange/testarch_generators/generate_testarch.py#L593

VPR was run with the following command-line:
build/bin/vpr /arch-defs/build/cla_cpld_v1/testarch_chipdb.device /work/logic/testdesign/1709032064290.netlist --arch_format fpga-interchange --circuit_format fpga-interchange --timing_analysis on --timing_driven_clustering off --echo_file on --netlist_verbosity 1 --pack_verbosity 2 --clustering_pin_feasibility_filter off --route_chan_width 100 --constant_net_method route --clock_modeling route --check_rr_graph off --timing_report_detail detailed --place_rlim_escape 0.95 --full_stats on --seed 1 --pack --place --route