llvm-capstone
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capstone-engine
llvm with tablegen backend for capstone disassembler
- Comment out unsupported code - Fill in operands See https://github.com/capstone-engine/capstone/pull/2349
WIP - [x] Fix `InstrInfoEmitter` conflicts. - [ ] Change `MCInstDesc` structs (those were changed to use less pointers). - [x] Move rest of the new emitting code into printer...
Hello, I was successfully able to use the ASUpdater.py script to generate the inc files for Arm. However, when I try the same with RISCV, I am getting the following...
When alias are emitter the priority is ignored. Only `priority = 0` (do not emit) is handled. Because of this we can not decide, which alias should be emitted in...
`x86` is currently not supported. But the reason is only a single not refactored backend. The `DisassemblerEmitter.cpp` emits the decoding tables via the class `RecognizableInstr` for `x86` or, for all...
We should add a CI test for PRs to check if all supported architectures still generate.
The `td` files of TriCore are missing in the source and need to be added. https://github.com/TriDis/llvm-tricore
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llvm with tablegen backend for capstone disassembler