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Generator of verilog description for FPGA MobileNet implementation

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Hello, thank you for sharing the engineering resources. I would like to ask, I used your pretrained weight files, put the storage.v and storage_bias.v files into the weight.txt file, and...

Hello, I admire you for doing such an excellent job. I would like to ask you a question: What should I do if I want to test the MobileNet algorithm...

![image](https://user-images.githubusercontent.com/49946568/105961136-13108c80-60b9-11eb-8ecd-cde3e86f63a2.png) Hi, there! Since every conv operation is followed by a Relu1 function, which can already guarantee the input values to the next layer are from the interval [0:1], I...

Hello, thank you for sharing the project.  I would like to learn whether the project design has published relevant articles. I want to know more about the hardware design and...