ice-chips-verilog

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I believe these work, but I haven't written test benches yet. Mainly posting them here so that they're there, and perhaps as a starting point towards merging it.

I expect you'd want test benches before you merge it, but I have almost no experience with Verilog and don't know that I'm well-suited to do it. Perhaps you could point me in the right direction?

Also I think the 74244 would probably want to use 2 BLOCKS of WIDTH 4, instead of WIDTH = 8.

Thanks for making this repo, it is very helpful. I'm using it to help design a CPU: https://github.com/jes/ttl-cpu - I do have a test bench system in that repo but it is very ad-hoc and bad. It is quite possible that I'll be creating more 74xx chips.

Hi James, thanks! Great to see your CPU project. That is going to be fun, and it's just what these parts are for :-)

I will create a tristate branch in my project to start adding these devices and others with the 1'bZ. If they work, that's great. But Yosys for FPGAs will not like those in a hierarchical design, so some changes will be needed eventually for that purpose.

Yes I will work on the (auto-generated) 74240, 74241, and 74244 and presumably 245. Happy simulating

Ah, I did not realise tristate parts wouldn't work on real hardware. I assumed Icarus Verilog would be exactly the same.

And actually I have just tried to build my CPU with yosys and it doesn't seem to like the #(DELAY_RISE, DELAY_FALL) syntax in the TTL files, is this expected?

1. Executing Verilog-2005 frontend: top.v
Parsing Verilog input from `top.v' to AST representation.
ttl/7402.v:21: ERROR: syntax error, unexpected ','```

It's expected. The ice-chips code may have to consider using an ifdef so the code is general, as for example: https://www.reddit.com/r/yosys/comments/6e9qka/either_parsing_or_ignoring_testbench_code

On Mon, Jan 25, 2021 at 7:56 AM James Stanley [email protected] wrote:

Ah, I did not realise tristate parts wouldn't work on real hardware. I assumed Icarus Verilog would be exactly the same.

And actually I have just tried to build my CPU with yosys and it doesn't seem to like the #(DELAY_RISE, DELAY_FALL) syntax in the TTL files, is this expected?

1. Executing Verilog-2005 frontend: top.v Parsing Verilog input from `top.v' to AST representation. ttl/7402.v:21: ERROR: syntax error, unexpected ','```

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The syntax error is on track to go away in the future! Pull request is being considered: https://github.com/YosysHQ/yosys/pull/2566

James, I'm pretty fired-up. I just realized due to looking things up this evening, in the Verilog manual the LRM, that the #(DELAY_RISE, DELAY_FALL) can be extended because there's a third timing parameter that can be used in simulation... A mysterious third parameter, that I never considered before, making it: #(DELAY_RISE, DELAY_FALL, DELAY_OFF). This provides a "turn-off" delay time when an output is going to high-impedance Z state.

The thing that's exciting is the devices I've done so far don't need it, they don't change: It's precisely the new tri-state devices that can have a DELAY_OFF parameter. So another thanks for prompting me to move forward on tri-state devices.

It's possible to peer into the future and CPU hobbyists may use the turn-off delay in very precise simulations that uncover potential bus contentions by examining GTKWave outputs in excruciating detail down to the microsecond and nanosecond. Let's see if you get into that.

Very exciting, that's good news about the yosys pull request!

Personally I'm not yet at the stage where precise timing details are important. I'm planning to change control lines on negative clock edges, ignore transient bus contention, take new values into registers on positive clock edges, and run the clock slowly enough that nothing too bad happens.

Syntax error will be gone now if you get the latest Yosys.