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Published 20 hours ago • verified publisher icon SciML

How to model ADC/DAC

Open jankap opened this issue 1 year ago • 1 comments

Is it already possible to model ideal and non-ideal analog-digital-converters (ADC) or DACs given the parts in the standard library?

Thanks :)

jankap avatar Mar 27 '24 18:03 jankap

Not quite :/

We are currently lacking

  • IntegerOutput (DigitalOutput). However, we do now support variables with integer type, so such an output connector could be implemented.
  • Handling the trigger condition could be done with an event, but events are currently known to have a number of bugs. If the triggering is periodic, it could in principle be implemented as a clocked system, unfortunately, support for this is not complete yet so this alternative is not yet available.

baggepinnen avatar Mar 29 '24 05:03 baggepinnen