SystemC-Components
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Minres
A SystemC productivity library: https://minres.github.io/SystemC-Components/
We get the `r_last` and `r_valid` for 2 cycles  I guess that it can be fixed, instead of https://github.com/Minres/SystemC-Components/blob/ed4a529680204b25797e35ab7c9875b1d3ada50d/src/bus_interfaces/axi/pin/ace_target.h#L420 putting it in `else` ``` if(this->r_ready.read()) { ... } else...
This size is not always correct: https://github.com/Minres/SystemC-Components/blob/ed4a529680204b25797e35ab7c9875b1d3ada50d/src/bus_interfaces/axi/pin/ace_target.h#L368 According to spec (Page. D3-187 [IHI0022H_c_amba_axi_protocol_spec.pdf](https://github.com/Minres/SystemC-Components/files/13441596/IHI0022H_c_amba_axi_protocol_spec.pdf) ) ``` The following transactions have a single read data channel transfer: - CleanUnique - MakeUnique -...
Hi Eyck, not sure if there is a bug in this line: https://github.com/Minres/SystemC-Components/blob/7d8a0173b219d684c80ba268086b31027d4a7402/src/bus_interfaces/axi/pin/axi4_initiator.h#L174C13-L174C13 In case we have e.g. `32B` wide bus, we want to have single `4B` write, with an...
At the moment only transactions with `gp.get_data_length() == gp.get_streaming_width()` are allowed. It would be beneficial if `tlm_target` would allow FIFO like accesses to resources.
Whether or nor write and read accesses to the sc_register are successful during reset should be configurable, at the moment there is no such check so all read and writes...
`axi::axi4_lite_cfg` does not work with bind_aw function because all signals are wired there, including `aw_user.bind(o.aw_user)`, although the width of aw_user in axi4_lite_cfg is `USERWIDTH = 0` This leads to the...
tested with conan2 by providing a conanfile.txt to provide dependies rather than relying on conan references inside the cmake files.
Hi, I ran into an issue when installing both SystemC and SCC into the same prefix location. When installing the library into a prefix, the generated `tlm` directory under `include`...
