Mike Thompson

Hi @RanjanThales, @JeanRochCoulon, @ASintzoff, this PR is now rather old. What is it's status?

> Hi Mike, The correct CI run for this merge is reported previously( https://gitlab.thalesdigital.io/riscv/core-v-verif/-/pipelines/1307923), however later the corresponding files are removed (cva6_tb.sv, cva6_core_tb_sram.sv), making this as conflicting files for merge....

Updated URL for the link to the waivers.

Hi @jstraus59 > I am wondering what the status is of the PULP tests, particularly the vectorized (now called SIMD) instructions. So far, I have found the bit manipulation, general...

Good points and questions @silabs-robin. Complexity creeps in step-by-step and eventually becomes problematic. Adding little-used features to the environment will over time lead to "bloat-ware" and few will remember what...

@JeanRochCoulon, @Gchauvon, @ASintzoff, can either of you answer @spidugu444's question?

Hi @spidugu444, does #1427 satisfy your request? If so, please close this issue. Thanks.

Is that #1288?

Hi @hasver, thanks for your issue. I will need some additional information. From your report my guess is that you are attempting to run simulations using the "core" testbench of...

Thanks for this @leemango1998! Would you be willing to generate a PR with the bug fix? Our process for accepting PRs is documented in [CONTRIBUTING](https://github.com/openhwgroup/core-v-verif/blob/master/CONTRIBUTING.md).