Matthias Koch

Trying the latest changes gives: - touch firmware.hex - Copied icestick_spi_flash_config.v to icestick_config.v - make ICESTICK.synth ``` yosys -DICE_STICK -q -p "synth_ice40 -relut -top femtosoc -json femtosoc.json" RTL/femtosoc.v Warning: Yosys...

I see, thank you: Up and running now, feels faster !

You have a lot of configuration options, I like that ! I usually have a folder for each target separately, and common folder(s) for the parts that can be reused....

A good place to draw the line is between CPU+RAM in a common module, with options for size/SPI execution/reset vector, and a separate target-specific Verilog file to wire in the...

The busy signals work this way: Processor sets address/data lines and pulses RSTRB or WMASK for exactly one clock cycle. In the cycle following the RSTRB or WMASK pulse, the...

Processor reads data from peripherals/memories one cycle after the RSTRB pulse or later when RBUSY goes low again.

@BrunoLevy Shall I prepare a pull request to add Quark variant with barrel shifter and Quark variant with barrel shifter and two-cycle operation to maybe RTL/PROCESSOR/EXPERIMENTAL ? Individua is still...

Thanks for your efforts! Failing of almost all alignment edge cases is no surprise for me, as they are implemented in a very small, but quirky way internally. But I...

Set parameter ADDR_WIDTH to 32.

I found that someone made an intro exactly to answer your question: https://www.youtube.com/watch?v=DtAwbKqLA5Y https://github.com/ShawnHymel/introduction-to-fpga