Digital-Logic-Sim-CE

Digital-Logic-Sim-CE copied to clipboard

Be compliant with Sebastian's community project guidelines

[]

We are missing some of this [points](https://github.com/SebLague/Misc-Project-Info/blob/main/Digital-Logic-Sim/Fork%20Guidelines.md) > If you've created a fork of the Digital Logic Sim project, and plan on distributing it, please follow these guidelines: > >...

AOx0

Chips not saving properly when chip doesn't have input AND output.

[{"_id":"67194b4d8794645d9a00da31","body":"this is for this and issue #48 \r\nthere are more problems with this than I initially expected. In addition to the issues pointed out, there is also a problem when trying to edit a chip with a clock in it. when I tried to edit a chip with a clock in it while editing another chip, things broke\r\n\r\n\r\n\r\n\r\n\r\n\r\nthis is me trying to edit a chip with a clock in it while I'm editing some other chip, you can see it by the name of the chip on the right.\r\n\r\nso there is a problem in loading the chip with a clock in general. I will check it out probably next month, for now, I want to leave a clarification.\r\n\r\nbeyond the bug. The clock isn't meant to be used in that way. currently, the simulation can only run the clock when it is in edit mode, and cannot save the value of the clock set. While it is possible to change this with enough work, I do not think it should be done. this is because you should instead design reusable chips with a clock input. in that way, you can design systems that can be synchronized by the same clock \r\n\r\nI hope this helps, and thank you for the issue ","issue_id":1715541512253,"origin_id":1366590347,"user_origin_id":52669351,"create_time":1672227860,"update_time":1672228165,"id":1729710925675,"updated_at":"2024-10-23T19:15:25.675000Z","created_at":"2024-10-23T19:15:25.675000Z"}]

Expanding on issue #48, when chips don't have an input and an output, not only do connections from such chips get lost, but in my experience, some gates within those...

BappoHotels

1Hz clock forgets its connections when compiled

[{"_id":"67194b4681864346730933a5","body":"This actually happens with any chips that do not have both an input AND an output. It has been an issue since the previous version","issue_id":1715541512297,"origin_id":1356944392,"user_origin_id":92649061,"create_time":1671412236,"update_time":1671412236,"id":1729710918854,"updated_at":"2024-10-23T19:15:18.853000Z","created_at":"2024-10-23T19:15:18.853000Z"}]

I made a simple togglable clock by sticking an input line and a 1Hz clock into an AND, which works until it is saved and exported. The new clock chip...

CDWimmer

ctrl-z

[{"_id":"67194b434febc2515c11b28b","body":"To further elaborate, IMO it should just be ctrl+z (undo) and ctrl+y (redo) to undo\/redo changes made to the chip you are currently editing\/making; however, once you have saved a chip I think you should \"lose\" the ability to undo the save, as allowing ctrl+z to undo saving would make the functionality somewhat difficult to understand","issue_id":1715541512330,"origin_id":1345636196,"user_origin_id":92649061,"create_time":1670786779,"update_time":1670786779,"id":1729710915715,"updated_at":"2024-10-23T19:15:15.715000Z","created_at":"2024-10-23T19:15:15.715000Z"},{"_id":"67194b434febc2515c11b28c","body":"I was already planning to add this feature using the command pattern. probably i will be able to do it in february","issue_id":1715541512330,"origin_id":1346751684,"user_origin_id":52669351,"create_time":1670859936,"update_time":1670859936,"id":1729710915721,"updated_at":"2024-10-23T19:15:15.720000Z","created_at":"2024-10-23T19:15:15.720000Z"}]

creating an editing history to enable ctrl-z / ctrl-^-z to undo / redo mistakes would be great

HannesGitH

disallow using chips that use the current chip `c` as a building block when editing `c`

[{"_id":"67194b6f97103643f30fba10","body":"E, I bet that bug has been here a while (though technically one could say it's not a bug)","issue_id":1715541512347,"origin_id":1345954402,"user_origin_id":92649061,"create_time":1670825971,"update_time":1670825971,"id":1729710959088,"updated_at":"2024-10-23T19:15:59.087000Z","created_at":"2024-10-23T19:15:59.087000Z"}]

do catch recursive loops early on so it wont cause problems later on in my case i just finished building a 8by8 bit multiplier but then noticed i was currently...

HannesGitH

"custom display chips" concept

[]

I had this idea a while ago, I really like the idea of the disp8 chip; however, there is no way for it to be used inside of another chip...

crispeeweevile

Enhancement - Give Options to remove some of the pre-saved chips

[]

Hi, It would be good to have an option where we can turn off the basic pre-saved chips. This would allow people to build XOR & OR themselves. I am...

SourSpoon

Various feature requests

[]

This is just a list of various things that would make DLS better ------------------------------------------------------------------ Changeable pin and wire colors like seen in the original DLS 7 segment displays that show...

ninjaguardian

Chip gets stuck in view mode screen on project load.

[]

When Loading a project it loads into view mode of a chip. everything is missing except for "ghost" input and output nodes. hitting the exit button only closes the project....

quiddler18

Regression in #79 - Pins should have their color updated alongside wires.

[]

This feature was useful for seeing the output of chips without having to connect them to anything. I'm not sure why the refactor removed it. I might have time to...

pudy248