David-Horner

On reviewing chapter 8 examples I believe it best to leave xnxti,x0 with clic.level > mcause.pil triggering. As previously suggested, use the least significant bit in rs1 or imm[0] to...

On 2021-02-10 2:54 a.m., Allen Baum wrote: > I'd file an issue (or, if you're ambitious, a PR) in the spec and see what > happens. Isn't this, riscv/riscv-isa-manual,  the...

@jrtc27 A most valid point. There are limited methods to guard against the risk of breaking code. The best appears to be the loader scanning for the low bit set...

@jrtc27 > JALR just calculates the address and masks of the low bit as a normal legalisation like RISC-V does all over the place. This calculation is unique among the...

@jrtc27 >Requires that the function returns never use jalr with lsb set in the imm field as well as prohibits presence of "auxiliary information" in lsb of pointers passed to...

My point is an ISA should be designed to avoid surprises. RISCV accomplished this extremely well in my opinion. It works in intuitive ways, when I see a feature and...

On 2021-02-16 5:40 p.m., Krste Asanovic wrote: > > This would be a backwards-incompatible change in the unprivileged > architecture. There is a much bigger barrier for unprivileged versus >...

@David-Horner >warning that you could be setting one half of the trap if you use it. The other half set by those who set the low bit of the branch...

Yes, the even-even and odd-odd cases appear to be generated when I looked at the TEST_JALR_OP(tempreg, rd, rs1, imm, swreg, offset,adj)  macro. But I was happy to defer to the...

The initial post on ISA-DEV is posted verbatim here: > The rationale document "The design of scalar AES Instruction Set Extensions for RISC-V" intentionally avoids discussing encoding. > > Nor...