UberDDR3
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AngeloJacobo
Opensource DDR3 Controller
When integrating Microblaze with UberDDR3, Vitis throws "Instruction overrun" error after configuring the FPGA. Ideally, the Microblaze fires up and waits at the first breakpoint at start of the program...
Hello. I'm trying to get this working on [Sechzig MX2](https://github.com/machdyne/sechzig), but I get the following error when building: prjxray.fasm_assembler.FasmLookupError: Segment DB CFG_CENTER_MID, key CFG_CENTER_MID.CFG_CENTER_LOGIC_OUTS_B21_9.CFG_CENTER_DCIRESET_LOCKED not found from line 'CFG_CENTER_MID_X46Y32.CFG_CENTER_LOGIC_OUTS_B21_9.CFG_CENTER_DCIRESET_LOCKED' Segment...
I am trying the NexSys_Video_example In file nexsysvideo_ddr3.v, you set .DQ_BITS(8), //width of DQ .BYTE_LANES(1), //number of DDR3 modules to be controlled Does this mean NexSys has just a 8-bit...
The line https://github.com/AngeloJacobo/UberDDR3/blob/main/testbench/readme.txt#L43C1-L43C5 mentions a testbench for the ddr3 module, but it doesn't appear in the repository?
How this project could be a first move towards an open source FPGA support for new memory use cases like memory tracing, emulation, ... ? https://asg.ict.ac.cn/hmtt/design/hmtt_v3/
OS: windows 11 Simulator version: Vivado 2024.2 Step to reproduce: 1. git clone to D drive 2. Run Vivado 2024.2 Tcl Shell 3. Run the following command: create_project UberDDR3 D:/UberDDR3...
At the latest main branch, I noticed the calibration to fail at a lower controller frequency (62.5 MHz controller, 250 MHz 4x clock, 200 MHz refclk). The state_calibrate can't go...
I recently wanted to play around with my FPGA again. I updated UberDDR3 to the latest master, but I couldn't get it to work anymore. After some trying around I...
Thank you for the GitHub resources. I'm currently working on POST#8 and have a question regarding Dhrystone performance. I'm using the Nexys Video board. While working on POST7 and POST8,...
Your implementation has a lot of error reports, like "System function calls are not allowed in constant functions [10.3.5(IEEE)]", which makes it difficult to integrate into cadense simulation toolchain. Just...
