Philipp Wagner

> Move package imports nice, now I understand how these warnings about global imports should be resolved. SystemVerilog remains a mystery at times. > Route debug ring as meander (currently...

> In a larger design the debug interconnect can become critical, because the mesh is actually mapped quite nicely as you would expect. Problem is that if you map them...

Ah, and https://www.optimsoc.org/docs/master/refman/configuration.html needs an update on `CTLIST` as well.

To avoid working on code which will be removed soon anyways we'll revisit this after @wallento merged his improved NA implementation. (see discussion in #112)

With a higher utilization I get a very similar timing violation also in a Nexys 4 DDR design system_2x2_cccc @ 50 MHz, hence we should invest a bit more time...

1. The console log looks wrong, you specify `speed=12000000` and it later says `Given speed 2000000 did not work`. Is this how it's displayed on your side? 2. Unfortunately the...

The cmake code is here: https://github.com/Kitware/CMake/blob/master/Source/cmExtraEclipseCDT4Generator.cxx

An easy way to install Eclipse is now available, as of #148

Prototype code in host-tile branch, configuration needs rework to be integrated into the CONFIG structure and more generalized.

We now have a single (multi-core) compute tile with Linux support. Having a setup with one "large" host tile and a couple compute nodes isn't there yet and mostly blocked...