Philipp Wagner

> Why are we even trying to discover always, initial, and function blocks? History, I guess :-) I don't think we have much use for these blocks ultimately.

I looked at the runs and that's what I'm getting with the QIS/Qrun flow with Questa 2023.2: ## VHDL-VHPI * Failure in testsuite: 'all' classname: 'test_iteration' testcase: 'recursive_discovery' with parameters...

VHDL+VHPI and Verilog VPI are clean now. We are left with failures in VHDL+FLI at this point. @AbdouTharwat, you wrote: > Finally regarding FLI and VHPI failures, we already opened...

@AbdouTharwat Yes, please send me a pre-release build of Questa to confirm the fix on FLI. For VHPI, we do see slightly different behavior during discovery as mentioned at https://github.com/cocotb/cocotb/pull/3306#discussion_r2082684649....

Finally! We're now running Questa 2025.2 and have a passing test suite! I updated the minimum version to select the QIS/Qrun flow automatically to 2025.2, since that's the first version...

> Is the impetus for this to compare against the values of scalar logic handles? Yes. Valid/ready/full/empty signals are something that's commonly used as bool, and getting a warning whenever...

@tgingold Do you have an idea what this problem came from? Looks like there were recent changes to the VPI interface in GHDL (https://github.com/ghdl/ghdl/commits/master/src/grt/grt-vpi.adb).

I opened #505 with what I think is the root cause of the problem, but I wanted to have this issue as well for others to find the error message...

Another file with the same symptom: https://github.com/lowRISC/ibex/blob/master/rtl/ibex_cs_registers.sv

This is an upstream verilator issue. Please report the issue there. You might want to upgrade to the latest Verilator release before.