fx68k
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FX68K 68000 cycle accurate SystemVerilog core
With respect to the following comments: ``` // Simulation problem // Sometimes (like in MULM1) DBH is not set. AU is used in these cases just as a 6 bits...
SRMC_RES is defined as: https://github.com/ijor/fx68k/blob/0602ee4627b10f301298f2673d826cdd6baa9327/fx68k.sv#L2305 So it must have a value of 6 and at least 3 bits. Then it is used in this if condition: https://github.com/ijor/fx68k/blob/0602ee4627b10f301298f2673d826cdd6baa9327/fx68k.sv#L2397 What is the...
Tested on Atari ST and fpgagen, no problems found so far.
No more LINT warnings under Verilator. New core size is less than 3200 LEs. Fmax on a Stratix 1S40 is 130 - 135 MHz