modifing c0_ddr4_ui_clk ???

[xiaoguoer]

Q1: the READ.md in hardware folder says "We will also use the DDR1 IP to create a clock for DnnWeaver. To do this, specify 150MHz as the frequency for c0_ddr4_ui_clk by double-clicking the IP and then specifying 150 MHz in the Advanced Clocking tab." But according to Xilinx, ratio between c0_ddr4_ui_clk and memory interface speed must be 1:4, and the minimum frequency of memory interface speed is 625MHz. So, how to modify c0_ddr4_ui_clk to 150MHz?

[hsharma35]

Apologies for the typo in the readme. Please use the addn_ui_clkout1 clock instead. I have updated the readme to reflect this.