Errors in sim and synth with fusesoc

[MateusFauri]

Hi! I'm using 3.12.2 python; 2.3 fusesoc and 2021.1 vivado.

I tried running these commands:

fusesoc run --target=sim barvinn

fusesoc run --target=synth barvinn

but i got these erros, respectively:

ERROR: Setup failed : Cannot find deps/MVU/ip/build/xilinx/bram64k_64x1024_xilinx/simulation/blk_mem_gen_v8_4.v in /home/fauri/Documentos/BARVINN

source barvinn_0.tcl -notrace
ERROR: [Common 17-69] Command failed: Part 'xcvu9p-flgb2104-2-e' not found
INFO: [Common 17-206] Exiting Vivado at Sun Mar 17 20:49:39 2024...
make: *** [Makefile:8: barvinn_0.xpr] Error 1
ERROR: Failed to build ::barvinn:0 : '['make', 'synth']' exited with an error: 2

Can anyone help me?

[hossein1387]

From the error, it seems the mem block rams are not generated. COuld you try to generate them using this script in MVU submodule?

[wagnersj]

Running the script mentioned by @hossein1387 does help address the error message that @MateusFauri is getting when simulating, however it leads to another series of error messages like this:

ERROR: [VRFC 10-2991] 'blk_mem_gen_v8_4_3_inst' is not declared under prefix 'native_mem_module' [../src/barvinn_0/verification/tests/conv/conv_tester.sv:83]

This looks like it is due to a change in a module name when the IP modules are generated. Xilinx tends to embed the IP version in the module name.

The problems encountered here can be solved by moving the MVU submodule up to a more recent version. The MVU submodule now does away with using the Xilinx IP modules for memory in favour of a more generic HDL memory instantiation. So, the Xilinx IP generation step is no longer necessary. Switching over to a newer version of the MVU submodule will require changes to the BARVINN verification code, for instance in conv_tester.sv. @hossein1387, can you make the needed changes on the BARVINN code? In tandem, I'll merge in the latest updates to the MVU master branch.

[shenbai12138]

Hi! I'm using 3.12.4 python; 2.3 fusesoc and 2023.1 vivado.

I tried running these commands: fusesoc run --target=sim barvinn --firmware=matmul.hex but i got these erros, respectively: ERROR: [VRFC 10-2991] 'blk_mem_gen_v8_4_3_inst' is not declared under prefix 'native_mem_module' [../src/barvinn_0/verification/tests/conv/conv_tester.sv:83] How should this issue be resolved now?Can anyone help me?

[wagnersj]

@hossein1387 Resolving this issue would be best done by updating to a later commit of the MVU submodule. Can you do this?

[hossein1387]

@MateusFauri @shenbai12138 Can you check now?

[shenbai12138]

@MateusFauri @shenbai12138 Can you check now?

yes，thank you