6522 dissection

[Rhialto]

Hi! Did you see the 6522 dissection that was done recently? http://forum.6502.org/viewtopic.php?f=4&t=7241 Did anyone check if there are insights from there that would cause the 6522 implementation here to change?

There is also this twitter thread https://twitter.com/RueNahcMohr/status/1571705526911905793 (which is about shifting in under T2 control) which seems to observe that a cycle of shifting a bit in starts with CB1 high, rather than low. Starting low is what your 6522 does (I tried it out), and also what VICE does. That also leaves CB1 high in idle state after 8 shifts / 16 timer underflows, so there is no need for an extra timer underflow to bring it to idle state again.

But, while comparing your 6522 with this scenario, I noticed a weird thing regarding the shift register. What I'm seeing is that on the falling edge of CB1, the shift register shifts (leaving bit 0 unchanged). On the rising edge of CB1, it corrects bit 0. This doesn't seem to match with http://forum.6502.org/viewtopic.php?f=4&t=7241#p93990:

In "22) shift register control", we have a 2:1 multiplexer controlled by ACR4. The output of said multiplexer goes into the LSB of the shift register as SR_IN. If the shift register shifts in (ACR4=0), the signal from the CB2 pad goes into the LSB. If the shift register shifts out (ACR4=1), the signal SR_CB2_Q goes into the LSB, means if the shift register shifts out it does circular shift.

I read that as saying that the shifting and the updating of SR bit 0 happens at the same time.

I used the m6522_tb.vhd testbench program where I replaced the body with

        begin
                wait for 2 us;

                -- Test shifting in under T2 control and observe CB1 (the clock output)
                -- clear interrupt flags
                reg_write(X"D","11111111");

                -- shift register
                reg_write(X"A","00000001");
                -- ACR: SR shifted in, speed set by T2
                reg_write(X"B","00000100");

                -- set T2 to 0002
                reg_write(X"8",X"02");
                reg_write(X"9",X"00");
                -- shift register
                reg_write(X"A","11111111");

                wait for 32 us;
                cb2_in <= '1';
                wait for 16 us;
                cb2_in <= '0';
                wait for 200 us;

                assert false report "end of test" severity error;
                wait;

        end process;

[Rhialto]

I just realised I got the testbench from another BBC FPGA project. I'll just attach it here. That is, if the github website isn't too stupid and emulating mswindows with its file extension madness. (yes, it is)

Makefile.txt m6522_tb.vhd.txt

[hoglet67]

Thanks for this input - when I next do some work on the BBC FPGA project I'll take another look at the 6522.

I was aware of the 6522 Discection, but haven't been following it in detail.