Digital
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hneemann
A digital logic designer and circuit simulator.
I am trying to draw a vector representation of the Digital distribution icon - with the RED and GREED outputs. It looks like it might be based on a couple...
When exporting verilog testbenches, module names are not properly escaped. For example, if the file "My-file" contains a test named "My-test" then the module declaration for the testbench will start...
Hi, hneemann, how are you? I made a project with Digital 0.24 that doesn´t run on Digital v0.30 (also works with v0.29). [MikroLeo_v0.19.zip](https://github.com/hneemann/Digital/files/15181079/MikroLeo_v0.19.zip) or https://github.com/edson-acordi/4bit-microcomputer/blob/master/Simulation/MikroLeo_v0.19.dig It appears that the description...
Hello. First time visitor here. First, I LOVE your project! It's amazing and very useful. For a project I am working on I am using Digital to model the gigatron...
Hi, Getting no answer to my comment in #464, I decided to open a separate issue to add some visibility to my efforts. As mentioned there, I'm currently working on...
If you would be willing to add this until perhaps one day these options are exposed to the end user, that would be amazing. You can see the details in...
Problem: It is hard to identify when an input pin is selected on a multiplexer. Solution: Highlight the input connection port in the multiplexer when the input is selected.
[74381.zip](https://github.com/user-attachments/files/16027210/74381.zip)
[7434.zip](https://github.com/user-attachments/files/16026689/7434.zip)
[747266.zip](https://github.com/user-attachments/files/16026528/747266.zip)