Digital
Digital copied to clipboard
hneemann
External File HDL generation fails with out-of-file line numbers
More often than not, when I'm trying to import a complex HDL code into the simulation, and I get a popup with a bunch of errors for a file which is only the extension (.v or .vhdl is the filename in the popup), and the line numbers are always outside of the last line of the file I'm trying to import.
Having temporarily replaced GHDL with a blocking program allowed me to inspect the actual line numbers in the TEMP folder before they got deleted, and all I can see is that Digital fails to parse the file, even though it is a valid HDL. Instead of stopping the assembly process with an error message, it is silently using the empty component name instead with a default port mapping, which ends up failing to assembly due to syntax error caused by the missing component name.
This happens both with VHDL and Verilog.
The parser used to extract the interface definition directly from the hdl code has some weaknesses. It does not cope with every file. In these cases, you can simply enter the interface definition into the corresponding fields by hand.
If errors occur that have larger line numbers than used in the file, it is because the interface definition is not correct. Special code is attached to the hdl code, which handles the data exchange between the simulator and the running hdl code, which is done via stdio, similar to piping applications on the console. If the interface definition is not correct, this interface code cannot exchange data with the actual hdl code.
Ah, you're right! I tried to instantiate a generic Verilog module, and as long as I type in the port mapping manually so it matches the default parameters then I can get it to work. But if I specify a different port size, then it fails (for obvious reasons, because I can't specify generic parameters).
As for the VHDL code, I'm really pushing the limitations of both VHDL, GHDL, and the UI of the External File module. Because I can't do
`ifndef EDA_SIMULATION_TOOL
`include "whatever_dependency.v"
`endif
in VHDL, I figured I could specify the dependency list via an at-file (that is, @listfile.txt containing filenames on each line). However the problem is that passing that at-file to the first command works as expected, but passing that same at-file to the 2nd invocation causes an error, because it tries to interpret the filenames as a module names (-e expects a module name as opposed to a filename), so that's where I got stuck. If I manually run the commands properly (that is, I pass the parameters as-is, except I also pass the at-file in the -a invocation) then I do get to a run interface (although GHDL does crash, but that is an issue in GHDL).
I could get it to work manually (without a crash) if I made a dummy relay (that is, just connect every input and output of a given module), GHDL -a every file into a fixed --workdir (including the one specified by the External File module), put the filename of the dummy relay into the Program code field, and put the --workdir into the GHDL Options textbox.
I guess I'm maybe pushing the limits of the Exernal File module a bit too much 😅
It would be great if I could at least somehow specify generic parameters (tried a generic init code, I guess it doesn't work for Exeternal File), and I'm fine with entering inputs and outputs by hand (due to the parser's limitations).
Oh also, it was really complicated to debug the issue, because any generated output is suppressed, and/or instantly deleted as soon as they are no longer needed. It would be great if there was an option to either redirect the output of GHDL/IVerilog to console/log file, and/or to keep generated files when an error occurs, so I can investigate what I did wrong without having to tediously run the commands manually, and also without replacing ghdl.exe with cmd.exe so I could copy off the generated files before they got deleted.