hlorenzi
Multiple Instruction 'virtual' OpCodes
Hi, Awesome tool. Took just a few hours to set up 80% of my 32-bit vCPU. Just a few sticking points, more pain points than show stoppers.
One was OpCodes that result in multiple actual instructions in machine code. It appears I can just output more bytes in a single def to get the same result. However, that requires duplicating bit packing over and over. Then, if I need to make a change to the bits of an instruction later, I'll have to find every virtual case where it was used and change that as well...unless I'm missing something.
If I understood it correctly, this is about reusing the output of some rules, right? We were discussing this on issue #52. I think this could be solved when I add #fn functions, that would allow you to move common code to a single place, and call it from multiple other places.
That would be fine as long as it could be determined by the value of operands. For example, a Load Immediate ASM instruction that uses two machine code instructions if the value cannot fit into 16 bits, otherwise it uses one instruction.
I've implemented something like this; see here: https://github.com/hlorenzi/customasm/issues/52#issuecomment-817425257
Do you think this is what you needed?