Muhammad Hadir Khan

BootROM support in the Arty A7 FPGA Prototyping flow

6

**Impact**: rtl | software **Description** Adding a support to attach a BootROM would allow the users to run their programs without using the JTAG interface initially. Just like the Freedom...

Cannot connect OpenOCD with the verilator simulator

5

**Tell us about your environment:** *Chipyard Version:* 1.4.0 **What is the current behavior?** I have generated a default configuration using the command below: ``` make CONFIG=TinyRocketConfig ``` Then invoking the...

**_chipyard version: 1.3.0_** Hello, I created a config and passed the SPI flash image using the following command: ``` make CONFIG=SmallSPIFlashRocketConfig +spiflash0=../../bootrom/bootrom.rv64.img run-binary-debug BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-sub ``` However, I get the following...

Difference b/w D$ and DTIM

1

I have disabled the d$ and created a scratchpad memory or so called a DTIM by providing the following parameters: ``` dcache = Some(DCacheParams( rowBits = site(SystemBusKey).beatBits, nSets = 256,...

openocd command stuck in mpsse_flush() loop

7

Hello, I created a basic rtl from chipyard that is correctly being mapped on the arty-35 fpga and uses the same jtag configuration as the freedom e30 configuration. I am...

The L1ScratchpadRocketConfig fails running rv64ui-p-add instruction

5

**_chipyard release: 1.4.0_** Hello, I am running the following command to build the simulator: ``` make CONFIG=L1ScratchpadRocketConfig ``` then executing an `rv64ui-p-add` test on the built simulator with this command:...

Hello, I have cloned the repository and running the command: ```scala sbt compile ``` causes the following error: _java.io.IOError: java.lang.RuntimeException: /packages cannot be represented as URI_

Value topName in class TreadleTester cannot be accessed in treadle.TreadleTester

4

Running sbt assembly in chisel-gui folder results in the following error on Ubuntu VM running on Windows 8: