12Mhz clock source from FTDI as external clock for FPGA PLL?

[fanoush]

trafficstars

Looks like the OSC_OUT from the FTDI goes to J9. Is it supposed to be connected back to FPGA as external clock source for the PLL to get stable clock? Could you perhaps document it a bit (possibly also with a few verilog lines) how to do it if it is indeed supposed to be used like that? Many thanks.

[olofk]

I would very much want to know this too. The HFOSC/LFOSC specs states a +-10% accuracy, which is pretty much, and might be problematic even with a simple thing as a UART

[fanoush]

Just answering myself. I finally tried and it seems to work. I've seen J8 somehow being connected on FPGA 101 board and examples took 12MHz clock from pin 35.

I did not find pdf schematics of the board howeverI connected J8 to pin 35 by wire and modified blinker example and indeed it worked and blinked much slower than with internal 48MHz. I guess pin 35 is chosen as it is global pin so the clock can be directly routed to any part of fpga (?)

I also tried to connect it to nearest pin 12 and used is as source for pll and derive 48MHz clock from it and it worked too and blinker example blinked again as with internal 48MHz clock. For that I used output of 'icepll -o 48 -m -f pll.v' command and used pin 12 as clock_in

So I am not sure if this is safe and whether there is some additional setting possible on the input pin so it would not e.g. put extra load on osc_out but it seems to work as is :-)

[fanoush]

I did not find pdf schematics

OK I found https://github.com/mmicko/workshop_badge/tree/master/workshop-gerber and uploaded badge.zip to http://www.gerber-viewer.com/ and it seems J8 simply goes to pin 35 so I guess that's it.