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                                            gsomlo

RocketChip with L2 cache - works in litex sim, works on digilent nexys video with cpu-mem-width is 64, breaks with 128

I added L2 cache to the `full` 64-bit width variants via https://github.com/litex-hub/pythondata-cpu-rocket/commit/018e94119d8777f2934ce3fb3ba8b02947cacc33 64-bit mem port width seems to be the only configuration supported by upstream with L2 cache, so using...

RocketChip with L2 cache - works in litex sim, works on digilent nexys video with cpu-mem-width is 64, breaks with 128

I found that removing https://github.com/enjoy-digital/litex/blob/master/litex/soc/integration/soc.py#L1635-L1650 (using Wishbone to up-convert between rocket and LiteDRAM) is a correct (if potentially suboptimal) workaround. One can use 64-bit (single-width) rocket variants on which the...

Migen outputs incorrect verilog in specific use-case

sort-of related question: in general, it is considered "good verilog" to use only blocking assignments in combinational (e.g., "always @(*)" blocks, and I noticed that migen uses nonblocking "