gsomlo

3.6: "Exercise: Mac as Object": solution suggests "you could also instantiate the Mac from above and connect the IOs to arguments". It'd be nice to actually provide a working example...

The thing I find particularly confusing is that, whether I've built my bitstream with `--cpu-mem-width 1` (LiteX provides AXIUpConverter) or with `--cpu-mem-width 2` (Rocket variant has matching 128-bit MEM port...

> booting Linux from SD with --cpu-mem-width 2 (128 bits) did work [...] on Digilent Nexys Video (no L2 cache) If you get a chance to try with `--cpu-mem-width 1`...

Ran some tests today. Since LiteETH isn't using DMA, I can `netboot` linux on both the 2x (128-bit) and 1x (64-bit) MEM port versions (on the nexys_video). Both are detecting...

On Tue, Sep 05, 2023 at 07:36:45AM -0700, Dolu1990 wrote: > > Proper fix would be to reimplement the litex AXI4 upsizer. > The interesting/confusing question I have is: How...

My plan moving forward is to remove any rocket variants with a mem port wider than 64-bit from `pythondata-cpu-rocket`, after first ensuring that the LiteX AXI up-converter is fixed (whether...

@dolu: I'm really excited about NaxRiscv and its potential to handle "real" distros, and, most importantly, being a potential replacement to Rocket :D I'm planning on finding a SpinalHDL tutorial...

For anyone who happens to find this thread, removing this block: https://github.com/enjoy-digital/litex/blob/master/litex/soc/integration/soc.py#L1635-L1650 (and using Wishbone instead of native AXI for the cpu-to-litedram width up-converter) appears to work correctly, if somewhat...

rocket uses tilelink internally, to connect and route between the cpu cores, cache, dma logic, and the externally accessible axi ports. i'm not entirely sure there's a good way to...

rocket handles cache coherence internally, between the dedicated dma-slave and memory-master axi ports, and the cpu cores' internal L1. this is the reason why litedram is connected directly to the...