Codegen should generate cleaner verilog when combining array update and conditions.

[hongted]

For code equivalent to

  next_state = if(condition) { state } else { update(state, val, index) } 

XLS may translate this into IR

array_index.9351: bits[12] = array_index(__state_0, indices=[index])
sel.10675: bits[12] = sel(condition, cases=[val, array_index.9351])
array_update.6404: bits[12][64] = array_update(__state_0, sel.10675, indices=[index])
next array_update.6404

With corresponding verilog

wire [11:0] array_update_15104[64];
assign array_update_6404[0] = index == 6'h00 ? (condition) ? __state_0[index] : val) : __state_0[0];
assign array_update_6404[1] = index == 6'h01 ? (condition) ? __state_0[index] : val) : __state_0[1];

This item is to update XLS with the end-goal of simplifying the final verilog output. To something like

wire [11:0] array_update_15104[64];
assign array_update_6404[0] = (index == 6'h00 && condition) ? val : __state_0[0];
assign array_update_6404[0] = (index == 6'h01 && condition) ? val : __state_0[1];

or to use always_comb blocks

  reg [11:0] array_update_6404[64]
  alwasy_comb begin
    array_update_6404 = __state_0;

    if(!condition) 
      array_update_6404[index] = val;
  end

This perhaps could be accomplished as an optimizer step or as a codegen step. If done at the optimizer/IR step that would be preferred as then the scheduler can correctly comprehend the circuit structure and delays.