Enable HW interface specification in DSLX modules

[vincent-mirian-google]

Motivated by the discussion from https://github.com/google/xls/issues/587 with @ted-xie.

Enable HW interface specification in DSLX modules: The interface specification of a parameter in a DSLX function or proc would generate an interface in the hardware description of the IP to interface with other IP when integrating the IP within a larger design.

[ted-xie]

Quick thought dump: really what needs to happen is that XLS-generated RTL should have the ability to flow-control the input and output interfaces. A simple ready/valid handshake with data should suffice, such as AXI-Stream with its TVALID/TREADY/TDATA. Having this type of flow-controllable interface is really crucial to enable XLS to be integrated in larger SoC projects.

[cdleary]

Also note relates to discussion in #578 -- "easy stitching of XLS components into pre-existing external-world environments" is something we can make more streamlined out of the box, given the places we've embedded in designs had dedicated integration bandwidth we didn't need it to be as "drag and drop" historically but this would clearly be enabling for more use cases.

[ted-xie]

I see #578 as a subset of this issue. AXI4 and other handshake-based memory-mapped IO protocols can actually be built with just a few FIFO handshake primitives (i.e. AXI4 can kind of be viewed as 5 separate FIFO handshake channels). Implementing the handshake protocols (ready/valid/data) should be a massive leap forward in integration capability.