SystemVerilog codegen should use `logic` instead `reg`

[proppy]

The two types are described as equivalent in the SystemVerilog standard:

6.11.2 2-state (two-value) and 4-state (four-value) data types

The keyword reg does not always accurately describe user intent, as it could be perceived to imply a hardware register. The keyword logic is a more descriptive term. logic and reg denote the same type.

And in Sutherland System Verilog for Design

** 3.3.2 SystemVerilog 4-state variables ** [...] Semantically, a variable of the logic data type is identical to the Verilog reg type. The two keywords are synonyms, and can be used interchangeably (except that the reg keyword cannot be paired with net type keywords, as discussed in section 3.3.4 on page 47).

See also https://github.com/lowRISC/style-guides/blob/master/VerilogCodingStyle.md#use-logic-for-synthesis