[enhancement] Add test points for mixed width operands in the delay model

[rw1nkler]

What's hard to do? (limit 100 words)

Currently, DSLX forces the user to cast operands of the arithmetic operations to the same type. However, for some binary operations even after casting one of the operands, the underlying original width is preserved in the IR and is used in Verilog code to perform the operation on the original operand widths, enabling the synthesis tool to create smaller hardware when possible.

The same type of optimization seems to be impossible on the scheduler level, as most of the test data points for the delay model use the same widths of operands. This will definitely affect operations like multiplication, but possibly other operations may benefit from that too (see LINK)

Current best alternative workaround (limit 100 words)

To obtain more accurate timing information for the proc, one can use the actual P&R data. However, there is no way to leverage the problem with "sub-optimal" delay model for the scheduler

Your view of the "best case XLS enhancement" (limit 100 words)

Extend the characterization process by providing more test points for the delay model