[enhancement] dslx should allow per-function naming of output ports

[proppy]

What's hard to do? (limit 100 words)

#448 #1427 #1429 discuss how to make output port names configurable globally (by adding an argument to codegen_main), but it would be nice to also have a way to specify those per function.

Current best alternative workaround (limit 100 words)

One could achieve something similar by specifying a different output_port_name for each function in xls_dslx_verilog rules, but this would have the drawback of scattering the information about a given function across multiple files: as the name is often more tighly coupled to the function definition (rather than the systemverilog context into which it is being integrated).

Your view of the "best case XLS enhancement" (limit 100 words)

@hzeller suggested we use #[codegen(...)] annotations, but we could also leverage the (recently proposed) syntax for named returns in Rust:

• https://internals.rust-lang.org/t/named-returns/18787
• https://github.com/rust-lang/rfcs/issues/2638
• https://crates.io/crates/named_return