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Support temporal logic assertions

Open hongted opened this issue 1 year ago • 1 comments

So that designers can utilize assertions akin to the assertions they are used to in SV, DSLX/XLS should support somthing akin to SV's LTL assertions.

Note that one complication is that unlike verilog, an XLS proc does not have an exact notion of a clock or about the latency/sequence of operations.

hongted avatar Mar 14 '24 21:03 hongted