DSLX DMA: Implement FIFO and CSR

[mczyz-antmicro]

DSLX DMA

This PR implements modules needed to build the DSLX DMA as described in issue #1208.

Ready for review

TODO:

• [ ] DSLX design and test
  • [ ] Main Controller
    • [x] Address Generator
      • [x] Based on CSR configuration, it produces a list of addresses
      • [x] Passes Unit test
      • [x] Control channels are integrated with top-level
    • [x] Frontend Reader
      • [x] Based on incoming addresses, it creates AXI-"like" transactions
      • [x] Transactions can be longer than 1
      • [x] Control channels are integrated with top-level
    • [x] Frontend Writer
      • [x] Based on incoming addresses, it creates AXI-"like" transactions
      • [x] Transactions can be longer than 1
      • [x] Control channels are integrated with top-level
    • [ ] Interrupt Controller
      • [ ] Expose Single Value Channels https://github.com/google/xls/issues/1281
  • [ ] Integration
    • [x] Test: Address Generators, CSRs, Frontends, GPF
    • [ ] Add FIFOs to test
  • [ ] CSR
    • [x] AXI Write Transaction (Data Width = 32, Transaction Length = 1) results in write to selected register
    • [x] AXI Read Transaction (Data Width = 32, Transaction Length = 1) results in read from selected register
    • [x] Address selected in the AXI RW Transaction is divided/multiplied by 4. (Linux driver calculates address in bytes)
    • [x] Number and width of registers is parametrizable, but set to 14x32bits as in the FastVDMA project
    • [ ] CSRs are correctly decoded and affect the state of the main controller
      • [x] Control Register
        • [x] Writer start and Reader start bit
          • [x] Information is passed to the Address Generator
          • [x] Bit resets itself unless in loop mode
        • [x] Writer sync disable and Reader sync disable
          • [x] Synchronization to external signal
        • [x] Writer loop mode and Reader loop mode
          • [x] run frontend transfers in a loop
      • [x] Status Register
        • [x] Writer busy and Reader busy bit
          • [x] Reads as 1 while frontend is busy with transfers
      • [ ] Interrupt Mask Register
        • [ ] Writer mask and Reader mask bit
          • [ ] Enables R/W interrupt
      • [ ] Interrupt Status Register
        • [ ] Writer interrupt and Reader interrupt
          • [x] Reads as 1 when interrupt has occurred (done)
          • [ ] Write 1 to clear interrupt
      • [x] Reader Start Address Register
      • [x] Reader line length Register
      • [x] Reader line count Register
      • [x] Reader stride between lines Register
      • [x] Writer start address Register
      • [x] Writer line length Register
      • [x] Writer line count Register
      • [x] Writer stride between lines Register
      • [ ] Version Register
        • [ ] DMA Version can be read from this register
      • [ ] Configuration Register
        • [ ] Different frontends can be selected
  • [ ] FIFO
    • [x] AXI Stream write (Transaction Length = 1) is correctly written to RAM at last free memory location
    • [x] AXI Stream read (Transaction Length = 1) is correctly read from RAM and memory location is freed
    • [x] FIFO of length L correctly handles N transactions when N >> L (overflow condition)
    • [ ] Debug integration test (2 FIFOs connected via GPF) #1237
  • [x] Mock Generic Physical Function
    • [x] Increment mode (all payloads are incremented by 1)
    • [x] Invert mode (all payloads are negated and truncated to 1byte)
    • [x] Used to test top-level view
• [ ] RTL Benchmark
  • [ ] Verilog generation
    • [x] CSR
    • [x] AXI CSR
    • [x] Frontend writer
    • [x] Frontend reader
    • [x] Address Generator
    • [ ] TBD (other blocks)
  • [ ] Frequency, power, area estimation
    • [ ] TBD

Implementation details

See README.md included in this PR for implementation details

Limitations

Current CI configuration fails:

• Bazel BUILD failed on an issue unrelated to this PR

WARNING: Download from https://mirror.bazel.build/repo1.maven.org/maven2/com/google/guava/guava/32.1.1-jre/guava-32.1.1-jre.jar failed: class java.io.FileNotFoundException GET returned 404 Not Found

• Main Controller Test fails with "DEADLINE_EXCEEDED" error due to the same issue as I had reported in https://github.com/google/xls/issues/1237. If you uncomment the last proc in the main_controller.x file, then the test passes. There are also other tests of the main controller that work standalone, but fail once at least 2 procs are uncommented
• AXI CSR IR optimization fails on "UNIMPLEMENTED" error. Please review BUILD rules and advise whether I should change BUILD rules or this feature will be implemented and we can proceed with merging this PR

[proppy]

@rw1nkler suggested that could also be a good standalone thing to review and land soonish.

[proppy]

@hongted mentioned that @grebe might be interested to look at the fifo implementation in that PR: https://github.com/google/xls/pull/1215/files#diff-e139db19aacd0f9c2a28123c053722349c6ef5ba135d288f53b92797112614dd

[mczyz-antmicro]

@proppy I agree, PR is ready for review. I force pushed today to include last changes and GH workflows.