Erroneous sky130_fd_sc_hd__dlygate4sd3_1 delay reported by timing files

[tdene]

The sky130_fd_sc_hd__dlygate4sd3_1, and indeed all other cells in the dlygate4sd family, appear to have discrepancies between their listed timing behavior and their behavior when simulated through spice.

The timing file delay can be found here.

Spice simulations were performed and recorded on the dlygate4sd3 25C tab of this spreadsheet.

In particular, note the high (~500ps) delay reported by the timing files when the cell drives a small load and has only small skew (optimistic conditions!).

Note the lower delay (~280ps) is seen when a FO4 spice simulation is performed (realistic conditions!).

Delay under optimistic conditions should not be higher than delay under less-than-optimistic conditions.

@msaligane @donghl17 @tspyrou @tdene agree that this issue should be investigated, such as by performing independent characterization of the specified cell family.