No timing libs for diode cells outside of sky130_fd_sc_hd standard cell kit

[tdene]

Expected Behavior

Each of the standard cell kits should have timing information under their respective cells/diode/ folder.

This timing information is imported when make timing is run, which is used by OpenLane to import pdks. Lack of these files causes the diode cells to exist in the library without any timing information. This discrepancy causes a crash in OpenLane's DIODE_INSERTION_STRATEGY = 3 algorithm which is provided through OpenROAD.

Actual Behavior

Only the sky130_fd_sc_hd standard cell kit has timing information under its cells/diode/.

Attempting to run a design through OpenLane with DIODE_INSERTION_STRATEGY = 3 will cause the tool to crash during its routing step.

Steps to Witness the Problem

1. Compare the hd library with the hs library.

Steps to Reproduce the Problem

1. Take a design through OpenLane with a sky130_fd_sc cell kit that is NOT hd
2. Do not change DIODE_INSERTION_STRATEGY from its default
3. Note the flow crashes during routing
4. Change DIODE_INSERTION_STRATEGY to 0 and re-run
5. Note that the flow no longer crashes during routing

Specifications

Latest version of the OpenLane repository was used to find this issue.