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Gate Level Simulation Doesn't Work As Expected for sky130_fd_sc_hd__dfbbn
Expected Behavior
Gate level simulation works by default.
Actual Behavior
Without FUNCTIONAL defined, gate level simulations use uses ".behavioral.pp.v" cells which does not work.
Steps to Reproduce the Problem
- Run a gate level simulation utilizing this cell "https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hd/blob/master/cells/dfbbn/sky130_fd_sc_hd__dfbbn.behavioral.pp.v". (Also the non power pins version)
- This behavioral version leaves several things unconnected and therefore does not work.
- Works when defining FUNCTIONAL.
Specifications
- Version: f6f76f3dc99526c6fc2cfede19b5b1227d4ebde7
- Platform: sky130_fd_sc_hd
I am not aware of any issues. Can you provide a specific error message? "leaves several things unconnected" is not a very helpful error report.
Sorry for the confusion. The exact issue is that several wires are undriven for example "RESET_B_DELAYED" on line 78.
https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hd/blob/ac7fb61f06e6470b94e8afdf7c25268f62fbd7b1/cells/dfbbn/sky130_fd_sc_hd__dfbbn.behavioral.pp.v#L78
This causes the flip flop to not work, and then our overall design fails simulation.
@mithro : The "specify" section was pulled out of all of the verilog files because iverilog does not handle timing. However, the $setuphold() statements work like buffers inserted in front of or after the gate. For example, in the above case, "D" is the gate input, but $setuphold() takes D as input and produces D_delayed; likewise for the delayed reset, set, and clock. To make the file iverilog compatible, if the naming is consistent, then it should suffice to remove the suffix "_delayed" from any signal in the verilog files. I'm not sure if there is any other fallout from doing that, and it needs to be confirmed.
It is probably worth checking whether or not iverilog handles the signals through the $setuphold() statement, even if it does not handle the actual timing. A bunch of warning statements out of iverilog would be preferable to a broken behavioral simulation.
Is there a way we could get the specify blocks with timing checks? It would be very useful to be able to run an sdf annotated gate level simulation
We got affected by this issue too. @RTimothyEdwards I would suggest to automatically generate non-delayed verilog versions of the libraries by open_pdks which are suitable for IVerilog (which remove the _delayed and remove any duplicate RESET wires)
