pcbdl
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PCB Design Language: A programming way to design schematics.
Similar to [CBOLD's ^ operator](http://cbold.com/cbold/refman/con_prac_two_port.htm). Instead of: vcc
While it's not really possible to define a part with the same refdes as another par normally. >>> Part(refdes="C1") C1 >>> Part(refdes="C1") Traceback (most recent call last): File "", line...
Together with issue #4, we should write a few tests for making sure refdeses do stay consistent. Something like a copy of servo_micro, and a ton of patches on top...
* [ ] "context" => "schematic" or something like that. This is really the thing that will be added upon to do hierarchies. * [ ] "defined_at" => "inspect" *...
Sometimes parts have pins that belong to groups (ex: SPI, SDIO). Those pins shouldn't really force the user to connect each pin individually, but there should be a way to...
In https://github.com/google/pcbdl/commit/d53d183b1eb44a23925aa264589c4f6681e8c1cf I added to the functionality that allows a Pin to be used instead of a Net for a lot of cases. Should write tests for that. Perhaps make...
It would help the migration out of Eagle into PCBDL significantly if there were an Eagle plugin that exports the schematic to pcbdl language.
See https://github.com/google/pcbdl/tree/d53d183b1eb44a23925aa264589c4f6681e8c1cf#bom Also don't forget about the populated part attribute.
Either from a netlist or a schematic. Both? https://github.com/google/pcbdl/tree/d53d183b1eb44a23925aa264589c4f6681e8c1cf#importing-from-traditional-eda-schematics
Generated SVG treats all nets with GND in it the same GND symbol, however it would be better to have different symbols for AGND and GND.