Project Request: iverilog

[capuanob]

I am requesting permission to integrate iverilog into OSSFuzz. I believe that this project is a good candidate for OSS-Fuzz integration as it serves as a preeminent compiler for Verilog HDL. As such, it directly preprocesses, parses, and compiles user-inputted VHDL programs, opening it up to a wide array of edge cases in capturing a complex language grammar and the potential for memory vulnerabilities (being written in C++).

[capuanob]

Approval has been received from upstream, as seen in this issue

[github-actions[bot]]

capuanob is integrating a new project:
- Main repo: https://github.com/steveicarus/iverilog
- Criticality score: 0.64605

[DonggeLiu]

Thanks @capuanob, may I ask who are the high-profile users of the project?

[capuanob]

@DonggeLiu Iverilog is the de-facto verilog simulator in academia and is used extensively in industry as well. In fact, the OpenRISC committee utilized iverilog in its prototyping of new hardware.

[DonggeLiu]

Thanks! I will report this to the panel : )

[DonggeLiu]

@capuanob The panel has approved, please feel free to proceed :) Thanks!

[capuanob]

@DonggeLiu Thank you very much! I will get started!