android-riscv64
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bionic/tests/sys_ptrace_test.cpp: add an instruction that writes more than 64 bits
we need to grab a V instruction to finish the missing piece of this test:
static void watchpoint_imprecise_child(Uint128_t& data) {
raise(SIGSTOP); // Synchronize with the tracer, let it set the watchpoint.
#if defined(__i386__) || defined(__x86_64__)
asm volatile("movdqa %%xmm0, %0" : : "m"(data));
#elif defined(__arm__)
asm volatile("stm %0, { r0, r1, r2, r3 }" : : "r"(&data));
#elif defined(__aarch64__)
asm volatile("stp x0, x1, %0" : : "m"(data));
#elif defined(__riscv)
UNUSED(data);
GTEST_LOG_(INFO) << "missing riscv64 instruction to store > 64 bits in one instruction";
#endif
}
vsetivli zero, 16, e8, m1, ta, ma
vmv.v.i v8, 0
vse8.v v8, (a0)
might be what we want? @negge