Add PLL to control clocks

[robertszczepanski]

This introduces PLL into HPS design with an additional option to enable/disable output clocks. It makes power consumption much higher. Initial tests with multimeter result in 70mW when CFU is disabled. It's ~30mW higher than version with DCC only presented in #597.

CI will fail because nextpnr-nexus requires a small fix to work. There is not needed tile generated into output .fasm. If you want to test it locally, build it as usual, prjoxide will fail to generate a bitstream with an error: thread 'main' panicked at 'No enum named PLL_LLC.MODE in tilegroup R28C1_PLL_LLC. Then go to generated .fasm and just search for PLL_LLC.MODE and remove a line that contains it. Run again prjoxide and it should generate a bitstream just fine:

cd soc/build/hps.hps_accel/gateware
prjoxide pack hps_proto2_platform.fasm hps_proto2_platform.bit