Gonsolo
Gonsolo
Currently the only target in the root Makefile is "verilog" (and "clean"). It would be nice to have a simple "Hello world" simulation for verilator. Currently there are the following...
``` diff --git a/CMakeLists.txt b/CMakeLists.txt index c67a6b0..98e3db2 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -20,7 +20,7 @@ endif (POLICY CMP0048) project(optix7course VERSION 1.0.1) -cmake_minimum_required(VERSION 2.8) +cmake_minimum_required(VERSION 3.25) if (NOT WIN32) #...
Since Chisel version 5 is the latest one, update the README accordingly.
### Background Work - [X] Yes, I searched the [mailing list](https://groups.google.com/forum/#!forum/firesim) - [X] Yes, I searched [prior issues](https://github.com/firesim/firesim/issues) - [X] Yes, I searched the [documentation](https://docs.fires.im/en/stable/) ### FireSim Version and Hash...
There should be a big fat warning that this is a very old version!
On branch main: > In file included from wb_port.c:19: > .../mgmt_core_wrapper/verilog/dv/firmware/defs.h:273: warning: "reg_debug_2" redefined > 273 | #define reg_debug_2 (*(volatile unsigned int*)(USER_SPACE_ADDR + USER_SPACE_SIZE)) > | > .../mgmt_core_wrapper/verilog/dv/firmware/defs.h:147: note: this...
There is not a single testbench for gfmpw-1c! 1. verilog/dv/README.md is an empty file 2. verilog/dv is empty except for the empty README.md; no testbenches, no tests. 3. make setup...
I tried bassoon-SEC-sustain.sfz from virtualplaying.com and it sound noisy. Can you fix that/tell what I can do? Thanks
I try to test my GFMPW-1 chip that I received last week. Connecting the board via USB results in the following dmesg (with a harmless warning, I believe): ``` [...